This relates to multiple gate semiconductor devices such as FinFETs (Fin Field Effect Transistors) and circuit applications of such devices as in a varactor.
A conventional field effect transistor (FET) is an essentially planar device having a gate structure that extends across the surface of a semiconductor such as monocrystalline silicon and doped source and drain regions in the semiconductor on either side of the gate. The gate is insulated from the semiconductor by a thin layer of an insulator such as silicon oxide. A voltage applied to the gate controls current flow in an un-doped channel that extends between the doped source and drain regions in the semiconductor beneath the gate.
The switching speed of the FET depends on the amount of current flow between the source and drain regions. Current flow depends on the width of the gate where width is the direction in the channel that is perpendicular to the direction of current flow. With the continuing demand for higher speed transistors for use in communication and computer equipment, there is a continuing interest in making transistor devices with wider gates.
FinFETs have been developed to obtain larger gate widths A fin is a thin segment of semiconductor material standing on edge, thereby making available multiple surfaces for the formation of gate structures. FIG. 1 depicts an illustrative FinFET 100 comprising four fins 110, 120, 130, 140. The fins have first and second major surfaces, such as surfaces 112, 114, that are opposite one another and usually are symmetric about a center plane that bisects the fin lengthwise. Major surfaces 112, 144 are often illustrated as being parallel as in U.S. Pat. No. 7,612,405 B2 or Pub. No. US2008/0128797 A1; but process limitations usually result in surfaces that slope outwardly from top to bottom of the fin with the result that the cross-section of the fin is trapezoidal in shape. FinFET 100 has a common gate structure 150. In other embodiments, a separate gate structure may be located on each surface of each fin. The width of the gate structures on each fin can be as much as T+2H where T is the distance between the first and second major surfaces of the fin and H is the height of the fin.
Doped source and drain regions are formed on opposite sides of the gates. As in a planar FET, a voltage applied to the gate controls current flow in a channel that extends between the doped source and drain regions in the semiconductor beneath the gate.
A common application of a planar FET is to provide capacitance in a varactor. In such an application, the source and drain of the FET are coupled together; and the source and drain serve as one plate of the capacitor and the gate serves as the other plate with the two plates being separated by the gate insulator.
FinFETs have the advantage that they permit device scaling to technology nodes such as 20 nanometers (nm) and smaller. Thus, it is desirable to be able to incorporate FinFETs in numerous circuit applications such as those that provide capacitance in varactors and other circuits. However, the narrow fin structure of the FinFET produces a higher parasitic resistance due to both the higher channel resistance Rch in the un-doped ultra-thin channel and the much higher (20×) source drain resistance compared to the source-drain resistance in a planar FET. See, V. Subramanian et al., “Planar Bulk MOSFETs Versus FinFETs: An Analog/RF Perspective,” IEEE Trans. Electron. Devices (December 2006); T. Cakici et al., “High Q and High Tuning Range FinFET Based Varactors for Low Cost SoC Integration,” 2006 IEEE Int. SOI Conf. Proceedings, p. 67, which are incorporated herein by reference in their entirety. The higher parasitic resistance reduces the quality factor, Q, of varactors formed from conventional FinFETs.
FinFETs can be connected as capacitors in multiple ways as described in the above-referenced paper of Cakici et al. In one embodiment, the gates of one fin are connected together to serve as a first plate of the capacitor and the source and drain of the fin are connected together to serve as a second plate. In a second embodiment that can be implemented with a FinFET with two independent gates, one gate is used as the first plate and the second gate as the second plate. The second embodiment provides a structure with a higher quality factor since it eliminates the parasitic source drain resistance losses. However, the second embodiment is not area efficient compared to the first because it requires four times as many fins as the first to provide the same capacitance. In addition, in the second embodiment, it is desirable to connect a tuning voltage to the fin; but such connection must be made through a large series resistance that is used to block transmission of AC signals through the tuning voltage connection. Such a resistance also consumes valuable device area.